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Conference Papers Year : 2016

Using reconfigurable multi-core architectures for safety-critical embedded systems

Abstract

With the onset of multi- and many-core chips, the single-core market is closing down. Those chips constitute a new challenge for aerospace and safety-critical industries in general. Little is known about the certification of software running on these systems. There is therefore a strong need for developing software architectures based on multi-core architectures, yet compliant with safety-criticality constraints. This paper presents a reconfigurable multi-core architecture and the safety-criticality constraints for airborne systems. The last section uses the current certification guidance to explain how the architecture can satisfy these constraints even with dynamic features activated.
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Dates and versions

hal-04026316 , version 1 (13-03-2023)

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Tom Guillaumet, Aayush Sharma, Eric Feron, Madhava Krishna, Ranjani Narayan, et al.. Using reconfigurable multi-core architectures for safety-critical embedded systems. 2016 IEEE/AIAA 35th Digital Avionics Systems Conference (DASC), Sep 2016, Sacramento, United States. pp.1-6, ⟨10.1109/DASC.2016.7777978⟩. ⟨hal-04026316⟩

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